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EUS FS - Alice II - Embeddable Single Board Computer

EUS FS is an "open" system board designed for industrial control and data acquisition applications. It is equipped with a 32-bit CPU working @ 200MHz (Etrax FS), Xilinx's gate array (Spartan 3E) and support electronics. A BSP package contains Linux operating system version 2.6, driver for communication with FPGA and peripheral devices. Example FPGA cores are available in source form, along with full board documentation -- schematics, layout.

The system is shipped with toolchains for ETRAX and MSP processors, FPGA design and synthesis tools are available from Xilinx free of charge.


EUS_II_topa EUSIIa_bottom

Product Brief

pdf_buttonEUS_FSPB rev 1.0

Feature List

  • Board dimensions 85 x 55 mm (3.35 x 2.175" )
  • 200MHz, 32bit Etrax FS processor
  • Up to 256MB SDRAM
  • 8 - 64 MB Flash
  • FPGA Spartan 3E - XC3S500-1600E connected directly on the CPU bus
  • Up to 64MB dedicated independent DDR SDRAM
  • Temperature, voltage and current consumption sensors implemented in MSP430 microcontroller
  • Unique board serial number
  • 10/100Mb Ethernet port
  • 1 x USB port
  • 1 x RS232 port (could be extended up to 4 ports)
  • JTAG interface for FPGA (Parallel Cable IV connector)
  • 91 separate input/output signals from FPGA
  • IO processor, peripheral or 72 general IOs from ETRAX processor
  • Single power supply voltage: 5V @ 700mA (depends on configuration and USB device consumption)
  • Boot over Ethernet
  • Opensource bootloader
  • FPGA initialization and communication tools
  • OS Linux 2.6, ftp, web server, telnet
  • All source code licensed under GPL or OHGPL
  • Royalty free application development software

Three basic configurations

  • Full system: Etrax FS + FPGA
  • Only Etrax processor
  • Only FPGA with Microblaze support

Data Sheets

File
Size
Description
Recommended PCB layout for Base-Boards
31.19 Kb
Recommended PCB Base-Boards layout
EUS_FS 1.0-Schematic
675.17 Kb
EUS FS Schematics, rev. 1.0
EUS_FS 1.1-Schematic
626.97 Kb
EUS FS Schematics, rev. 1.1 New!
EUS-FS-1.0-PCB
225.18 Kb
PCB overview and board dimensions
EUS_FSPB
437.57 Kb
Product Brief

Board Support Package

Link
Link Description
Installation manual
Installation Manual
BSP Linux
BSP Packages for Linux
BSP Windows
BSP Packages for Windows (VMWare Image)

Evaluation Kit - Starter Board

Feature List

  • Board dimensions 160 x 100 mm (6.3 x 3.94") - Eurocard compatible
  • Evaluation Kit for EUS-FS boards
  • 2 x IO connector 96 pin, DIN41612 Class 3 compatible, IO signals +5V compatible and protected
  • 1 x 10/100Mb Ethernet connector
  • 2 x RS232 Serial connectors
  • 2 x JTAG interface for FPGA and ETRAX FS (Paralel Cable IV connector)
  • 1 x JTAG interface for MCU MSP430
  • 1 x VGA analog video connector
  • 1 x USB host connector and 1 x USB peripheral connector
  • 1F high capacitance for RTC back-up
  • 8kB FRAM I2C memory
  • Keyboard with 5 buttons inclusive with LEDs + Reset button
  • Single power supply voltage 5V, socket for EIAJ standard power plug

 

Link
Link Description
pdf_buttonEUS_FS_START 1.1
Starter Board Schematic New!

Reference Designs

Link
Link Description
FPGA Registers
Provides an access into FPGA's registers
DDR Memory test
DDR Memory test based on Microblaze EDK 9.1
Blinking LED
Shows how to make LED blinking.
Keys and LEDs
Shows using of buttons to control LEDs.
VGA demo
Shows how to use VGA interface.
Registers connected to BUS interface
Shows how to connect registers into BUS interface.

Applications

Link
Link Description
MMC/SD card connection
Introduces how to connect MMC/SD card into EUS FS board

HOW-TOs

Link
How to compile C program
How to get into U-Boot
How to change MAC address
How to change IP address
How to load design into FPGA
How to load design into boot partition for FPGA
How to reflash linux kernel image
How to reflash root filesystem image
How to connect to the board via serial port
How to connect to the board via ethernet
How to copy files into the board via WinScp / Scp
How to install and use Board Support Package
How to compile FPGA design using XILINX ISE
How to compile FPGA design using Makefile

 

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